With the development of the Internet, traffic of a telecommunications backbone network is rapidly growing by 50% to 80% each year. At the beginning of the year 2011, the IEEE 802.3 working group started to collect a bandwidth development requirement after a 100GE Ethernet interface. With regard to the development of network bandwidth in the future, the IEEE 802.3 working group considered that network traffic in the year 2015 could reach 10 times what it was in the year 2010. According to a preliminary analysis, there would be two rates of 400GE/1TE for an Ethernet interface in the future, and such requirements would appear and begin to be applied in the year 2015 and the year 2020, respectively.
As a transmission rate increases, a high frequency loss of a signal on a high-speed transmission link increases; therefore, intersymbol interference affects an indicator such as signal quality or a bit error rate. However, currently, a decision feedback equalizer (English full name: decision feedback equalizer, English acronym: DFE) is universally used on a receive side of a high-speed interface, which embodies distortion caused by white noise on the link in a form of an error burst. Therefore, the industry begins to study how to perform error correction on a bit error in the Ethernet by using an FEC algorithm.
In the prior art, an interleaver (English: Interleaver) in a sending device writes by row and then reads by column a section of data on which FEC encoding has been performed. The sending device then sends, to a receiving device, the data read by column. For example, when data 1 on which the FEC encoding has been performed includes data units U0 to U4, and data 2 on which the FEC encoding has been performed includes data units U5 to U9, the 10 data units are written by row, and it is set that each row includes five data units, and then written data is shown in Table 1.
TABLE 1U4U3U2U1U0U9U8U7U6U5
The data shown in Table 1 is read by column, and then data shown in Table 2 can be obtained.
TABLE 2U9U4U8U3U7U2U6U1U5U0
The data read by column is sent to the receiving device. The receiving device performs an operation inverse to that of the sending device on the received data, and in a normal case, the data shown in Table 1 can be obtained again.
During a transmission process, a bit error may occur in the data read by column and shown in Table 2, for example, a bit error occurs in the three successive data units U6, U2, and U7. The receiving device restores an arrangement order of the data units in Table 3 to that shown in Table 1. Therefore, the three successive data units U6, U2, and U7 are not successive any longer. In other words, a probability that multiple error codes occur in one code word decreases. In this way, error correction pressure of an FEC unit in the receiving device can be reduced to some extent.
However, in the foregoing method, such a special interleaving manner of writing by row and reading by column needs to be performed. In this interleaving manner, a section of data needs to be written before the section of data begins to be read, which generates an obvious delay.